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Hi, all!
Is it possible to use cv2.findContours() with Vitis vision Library?
1. I didn't find this function in list:
https://github.com/Xilinx/Vitis_Libraries/blob/master/vision/docs/src…
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When running more that one job inside a pod cannot submit more than one job reliably. If more that one job is summitted in succession we get a input output error. This problem can be mitigated by xbut…
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Hello,
i've searched the Aliexpress for absolute cheapest FPGA boards and i've found very cheap devices that i think might be worth supporting:
- Noname chinese bargain FPGAs
- https://hackaday…
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Hi ,
i am unable to synthesis the accelerator , synthesis results in following errors and warnings:
ERROR: [HLS 200-70] Synthesizability check failed.
command 'ap_source' returned error code
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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Tried to execute code (the one in the Xilinx repository) with newest version of RFNOC after having applied your patch to uhd-fpga. However the design does not synthesize.
I believe that the changes…
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Hello, I saw the issue you posted before, as shown below. I have the same problem as you did. My MC only supports DFI, but I want to verify it on xilinx MIG. I have learned some transfer processes bef…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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This is an inquiry to the wider audience who are working on getting NVDLA running on a FPGA platform--we'd like to share what we are doing and check progress on other groups out there .
we are putt…
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It looks like Xilinx removed the SUSPEND mode from 7-series FPGAs, so there is no explicit sleep mode to be triggered.
Clock gating (stopping the clock while not in operation) is still an option and …