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There is some bug when working out my SystemVerilog project. After reduction, the minimal sample that triggers this error could be:
```systemverilog
typedef struct packed {
logic a, b;
} test_t;
…
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I would like to add "late-connect" semantics to the Python bindings. That is, be able to create an arbitrary operation without having `Value`s for each operand. The user would be able to connect them …
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Different take than the VHDL request - I'm instantiating the SV output in a VHDL design. If I take the SV package and make a VHDL equivalent (records that match the structs), I'm able to keep the SV c…
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There has been no update for 2 years. The latest AMD/Xilinx is 2023.2 I think you support 2021.2.
Are there any plans to update this?
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I've been trying to run the https://github.com/SystemRDL/RALBot-html/blob/master/example/turboencabulator.rdl example to see if I can get Ordt to parse the same file.
As it appears, Ordt fails to p…
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Background: We are bumping our firtool version. See https://github.com/chipsalliance/t1/pull/734
# Description
After the bumping, our workflow breaks as if all `$stop` statements are discarded. …
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Now cast to builtin types will be syntax error.
```
Expression11: Expression12 { As ScopedIdentifier };
```
The simple way to support it:
```
Expression11: Expression12 { As ScalarType };
…
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The code below sets bit 3 of all members of array a. I should print '8888' (tested with vcs).
However, I got this error running with "iverilog -g2012"
> mda.v:8: error: A reference to a wire or r…
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C++ のサイズ0の配列のように、幅ゼロのバスを定義できると嬉しいです。
SystemVerilogの場合 たとえば 1対N マルチプレクサ を
```
module multiplexer
#(
parameter int N = 2,
localparam int S = $clog2(N)
)
(
…
ryuz updated
6 months ago
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Sv2v version 0.11.0 is represented by vectors when converting the structure, and the name of the field cannot be seen in the converted Verilog code, resulting in poor readability, can the name informa…