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Following the guide in readme.md to generate bitstream for zc702_fmcs2 board with code version 8cdaf54. No any code change. It fails.
Host OS: Ubuntu LTS 22.04 with Vivado Simulator 2018.3
Below i…
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Currently we don't have a wishbone slave implementation, which is required if we want to perform any memory accesses. I've researched our options with regards to fixing this and they're as follows (in…
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I have installed IVerilog in Mac in:
/usr/local/bin/iverilog
with:
brew install iverilog
I have tested in terminal or from editor VSCode, included VCD viewing with GtkWave, without problems.
I …
j054n updated
2 years ago
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Hi, your README might be a little confusing, so may I ask you three questions?
First of all, your program is written in Haskell, right? So what platform do we need to use to reproduce your program? w…
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This is something I found with:
- OS Fedora 29 (64-bit)
- python V3.7.2
- cocotb V1.7.2
- Verilator 5.006 (build with gcc version 8.2.1 20181215 (Red Hat 8.2.1-6) (GCC))
Verilator seems to b…
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While reverse engineering an IC, a flop flop nmos representation was extracted from the layout. The icarus simulation provides an incorrect response to its functionality. This testing was re-simulated…
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Icarus Verilog cannot be used for simulation with fx68k, even when using the -g2005-sv option. As Icarus Verilog is the main FOSS tool for verilog simulation, it would be good to be able to use it.
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Hello
I want to simulate simple system hello test using verilator,but after executing ./build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system [-t] --meminit=ram,./examples/sw/simp…
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Currently we emit an error like:
"Output out, instance #0 not found in Verilog simulator output".
We should raise an error indicating that there was an X in the output until we handle X properl…