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After I added a module to pulp_soc and synthesized PULPissimo for zcu102 I'm struggling with openocd, this is the result of the debug view. I've installed the patched version of openocd through pulp-s…
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Hi,
I am facing a problem while understanding RISC-V signals.
Where can I get a detailed document for understanding the RISC-V core?
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## Overview
1. Bump the polkavm(-*)? dependency everywhere.
2. This will require you to update the executor as it is using polkavm to execute runtimes.(first link)
3. Update the wasm-builder to u…
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I wonder, should this be specification also be mentioned at the RISC-V website's spec section at https://riscv.org/technical/specifications to make it known more widely?
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Hello,
we're using the cv32e40p on FPGA and building FW for it using the corev-gcc toolchain. We added a custom instruction and I could add it to corev-gcc so we can actually use it (btw, thanks for…
rcvlr updated
3 months ago
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As requested by @0xdaryl , we should be able to set up a cross-compilated/emulated RISC-V CI testing environment in OpenJ9 for RISC-V before the hardware is attached to the project, which is similar…
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Using Ubuntu 20.04 LTS here on Virtual Machine, Error pops up with Installing VPM using curl. (Maybe the architectural difference)
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[The comment about RISC-V devicetree extension order](https://github.com/google/cpu_features/blame/main/src/impl_riscv_linux.c#L25) is not aligned with the URL in the comment.
This is mea culpa, be…
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### What would you like to be added?
Hi,
Please can you add riscv64 support on your release ?
Also have riscv64 servers if you want to work on it ?
Best Regards
### Why is this needed?
Becau…