openhwgroup corev-binutils-gdb issues

openhwgroup / corev-binutils-gdb

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issues

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#119 MaryBennett opened 4 days ago
2
SIMD: fix issue #117

#118 forceofsystem closed 4 weeks ago
2
Error not generated for cv.shuffle.sci.h with wrong Imm6 value

#117 pascalgouedo closed 4 weeks ago
3
Additional warning for clipr/clipur instructions

#116 pascalgouedo closed 1 month ago
1
Roll forward - 19th March 2024

#115 Slattz closed 3 months ago
0
Roll forward

#114 MaryBennett closed 5 months ago
0
Fix incorrect opcode for cv.elw

#113 MaryBennett closed 6 months ago
0
incorrect opcode generated for cv.elw

#112 superflyers closed 6 months ago
1
HWLoop relocation error

#111 pascalgouedo closed 6 months ago
4
Roll forward

#110 MaryBennett closed 7 months ago
0
simulator

#109 rcvlr opened 7 months ago
2
Fix Zca always opens the compress flag.

#108 pz9115 closed 6 months ago
2
SIMD: fix issue #104

#107 MaryBennett closed 5 months ago
0
tablejump section (__jvt_base$) need be aligned on a 64-byte boundary

#106 Pudding2018 opened 8 months ago
1
Fix "missing prototype" warning

#105 MaryBennett closed 8 months ago
0
Handle the range of the immediate shift and extract instructions

#104 melonedo closed 5 months ago
3
Renaming of cv.slet to cv.sle

#103 MaryBennett closed 10 months ago
2
Changed post inc instructions mnemonic

#102 MaryBennett closed 10 months ago
3
Update naming for xcvmem instructions

#101 MaryBennett closed 10 months ago
3
Naming of cv.slet

#100 MaryBennett closed 10 months ago
1
CORE-V: All instructions in binutils are currently using lowercase

#99 NandniJamnadas closed 10 months ago
1
Getting CORE-V ready for Upstream

#98 NandniJamnadas opened 11 months ago
2
CORE-V: SIMD Update: cv.or.sci[.h,.b], cv.xor.sci[.h,.b], cv.and.sci[.h,.b], cv.avgu.sci[.h,.b]

#97 NandniJamnadas closed 11 months ago
2
cv.avgu and cv.srl/sra/sll instructions out of sync

#96 melonedo closed 5 months ago
3
CORE-V: SIMD Update - Removal of redundant SIMD mask macros in riscv-opt.h

#95 NandniJamnadas closed 11 months ago
2
CORE-V: Remove versioning support for XCV Extensions

#94 NandniJamnadas closed 1 year ago
3
disassembler translate cv.insert machine code wrongly to cv.muls

#93 superflyers closed 1 year ago
3
CV32E40Pv2 MAC pseudo-instructions

#92 NandniJamnadas closed 1 year ago
2
CV32E40Pv2 Update SIMD Instructions and Test

#91 NandniJamnadas closed 1 year ago
3
CV32E40Pv2 Update Post Increment Load/Store

#90 NandniJamnadas closed 1 year ago
2
The immediate field of shift instructions should be unsigned

#89 melonedo closed 1 year ago
1
Zcmt relaxation of single *.S-source bare metal code

#88 silabs-hfegran opened 1 year ago
3
Post-Increment Register-Immediate Load should be updated

#87 ChunyuLiao closed 1 year ago
2
RISC-V: Fix .option arch compatibility with zc*

#86 simonpcook closed 1 year ago
3
Using hexadecimal value for instruction signed immediate seems restricted to positive values.

#85 pascalgouedo closed 1 year ago
2
ld segfault when linking .S assembly file

#84 silabs-hfegran closed 6 months ago
5
RISC-V: skip unrelated relocations in table jump relaxation phrase

#83 linsinan1995 closed 1 year ago
5
Incorrectly compiles functions in newlib with Zcmt-ext

#82 muxiff closed 1 year ago
2
RISC-V: Fixed the overflow values for cv relocations

#81 MaryBennett closed 1 year ago
2
Fixed linker failer due to cm.jt/cm.jalt change

#80 MaryBennett closed 1 year ago
2
Does Event Load Word need a custom relocation

#79 jeremybennett closed 1 year ago
3
RISC-V: update match_func of cm.jt/cm.jalt to spec 1.0.

#78 linsinan1995 closed 1 year ago
3
Zcmt issues with latest binutils build

#77 silabs-hfegran closed 1 year ago
1
Remove 'xcv' extension

#76 CharKeaney closed 1 year ago
6
Update CORE-V Extension name prefix from 'xcorev' to 'xcv'

#75 CharKeaney closed 1 year ago
6
CV32E40Pv2 SIMD 6-bit Unsigned Immediate + Renamed SIMD GAS Tests

#74 NandniJamnadas closed 1 year ago
9
Linker does not test HW loop offsets are in range.

#73 jeremybennett closed 1 year ago
4
Updated relocation tests with cv32e40pv2 encodings

#72 MaryBennett closed 1 year ago
2
Changed the immediate order in bit maipulation instructions

#71 MaryBennett closed 1 year ago
2
Updated hardware loop instruction encodings

#70 MaryBennett closed 1 year ago
3