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## Steps to reproduce the issue
This file compiles successfully in vivado
```verilog
module foo (
.another_name_for_a(a),
.another_name_for_b(b),
c
);
input a;
input b;
outp…
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#### Expected Behavior
Placement timing should sample a variety (all?) of block types when forming delta matrix,.
#### Current Behavior
Delta delays are sample at most 6 types of blocks, and …
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Jared added support for parsing System Verilog Assertions (SVAs) in VL. It'd be nice if these SVAs could have meaningful semantics in SV. Furthermore, it'd be good SVAs could be transformed into Ver…
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Hello,
I am using `verible-verilog-syntax` to process verilog files and it is working great! I just have one question,
Sometimes my code contains looks like so:
```
`ifdef ABC
...some c…
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Example:
```SystemVerilog
bind a b c (.d);
```
(e.g. [real world example](https://github.com/lowRISC/ibex/blob/master/vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_inv_hamming_76_68_bind_fpv.sv…
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A subset of the lint rules shouldn't apply to Verilog (2009) source files, e.g. `forbid-defparam`.
This multi-part task is to introduce a mapping of lint rule to dialects.
For now, I think two dia…
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Block selection via the search dialog currently only accepts clustered block names, and clustered block IDs.
1. Ideally it would also accept primitive names (atom netlist names) and highlight the b…
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Hi,
I want to restrict my application to only verilog programs and not system verilog, can you help me figure out the grammar specification for only .v files?
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In my understanding of verilog code, it seems like `(prescale * 8) * 9 bits * baud = Fclk`.
`*8` because `prescale_reg
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It would be good if the following pages;
* https://docs.verilogtorouting.org/en/latest/vtr/benchmarks/#titan-benchmarks
* https://docs.verilogtorouting.org/en/latest/tutorials/titan_benchmarks/
…