-
I'm tring to install the cocotb on MSYS2 environment but it fail on binaries build on missing 'unistd.h'.
```
"C:/Microsoft Visual Studio/2019/BuildTools/VC/Tools/MSVC/14.29.30133/bin/HostX86/x6…
-
Thanks for taking the time to report this.
Can you attach an example that shows the issue? (Must be openly licensed, ideally in test_regress format.)
I've modified t_class_uses_this.v to show t…
-
1. If spinalsystemverilog is used, Verilog is generated after mergertlsource instead of SystemVerilog
2. If spinalconfig is configured as onefilepercomponent, and only report blackboxesSourcesPaths. …
-
I am using wsl system. In the post synthesis simulation, when i try to use the Icarus Verilog simulator I got this error :
tsp@DESKTOP-S7PFFHU:~/Projects$ iverilog -o example.vvp example_synth.v …
-
The new version of Verilator now displays the column number in the error message. This causes flycheck to parse the Verilator output incorrectly. Possible fix:
``` diff
--- a/flycheck.el
+++ b/fl…
-
Question: our design flow organizes each standalone hardware block in its own repo. It will manage its design files in an `hdl/` directory, and its testbench in a `tb/` directory. The idea being that …
-
Hi,
Now I'm using Cocotb for my HDL projects and I ran into this problem:
In my project I use source files in two languages at the same time: Verilog and VHDL.
But as a result, I’m faced with a …
-
when I run command: make buildfile CONFIG=TinyRocketConfig. Errors below came out and terminate in the end
[error] INFO: unable to compile data_arrays_0_0_ext using SRAM2RW64x4 port count must …
-
Hello, my plan is to extend the functionality of this tool (by adding branch predictors and L2 cache for start) but I have issues in loading and building the project on QtCreator and start developing …
-
I'm new to this repo, and failed to find the tests signatures, results. I think these were provided at some point .. What do I check/compare with my run results?