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Support for Microsemi's Physical Design Constraint File (*.pdc file extension) for Libero SoC (for the following FPGA family: PolarFire, SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusio…
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Hi, Below CVEs are reported in the latest 1.6.19 image. These needs to be taken care as part of governance as memcached is being used across our k8s containers
CVE-2019-8457
CVE-2022-1304
CVE-202…
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Hello, this is actually more of a question than a feature request. I did follow the discussion in the Ariane Cache support issue #61. One thing is still not clear to me.
Can I follow the same conf…
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I've been implementing JTAG-DTM and DM lately, and have been wondering about automatic target identification and discovery methods. I skimmed through public discussions I could find around DM, DTM and…
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Hi,
I am attempting to perform phase coherent readout using a ZCU216, with a bitfile slightly modified from the q3diamond. My DAC and ADC modules are:
```
Board: ZCU216
Global clocks (MHz): tPr…
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After flashing with using branch '9-support-for-jetson-orin-nano', GUI or display not working.
- minicom working and looks like it's flashed successfully.
- When using 'ACPI' on BIOS rather than '…
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Hello,
Thanks for this great work, I appreciate the whole work. It is extremely beneficial.
Actually,I removed the constraint file of KC705 board, and I used the constraint file of VC707 board, and …
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Based on chipyard I generated a SoC with DRAM and SPIFlash, next I want to map this SoC to FPGA board. I will not use the JTAG interface for the time being, and directly read and load the executable f…
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when I run install.sh, I got the following errors (all other steps are good). I am using the latest code as 02/19/2023
```
3. Main software...
mkdir: cannot create directory ‘build’: File exists
[…
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Hello,
I updated litex to retrieve last changes but I got an error with the parser.
Here is what I do :
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCA…