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**Is your feature request related to a problem? Please describe.**
I am currently working on implementing the [RVVI](https://github.com/riscv-verification/RVVI/blob/main/source/host/rvvi/rvvi-trace.s…
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Hi, are there any plans to create spec-compliant debug interface for VexRiscv? Although current debug interface is really nice and has nice performance it would be great to have standard solution in p…
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Hi,
I now have Crave integrated and working in my "elaborate" UVM-SC testbench. Crave variables are being randomized subject to the Crave constraints I put in place - using the experimental API as …
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Hello,
I cannot find a way to reproduce this crash, but it happens may be once or twice in 1000+ invocations of the proc call that does the plotting using ggplotnim.
Here's what the sigusrdump.o…
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What would you like added/supported?
I would like to know on how can I add source annotations on the generated C++ Source files mapping it back to Verilog and SystemVerilog RTL sources.
Can you at…
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I'm trying to use this code in a Spartan 6 board, however ISE14.7 does not support System Verilog.
Vivado supports SV but not Spartan 6 family :-(
I tried to translate this code to Verilog but packe…
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Using the information below create a LEMA tutorial:
1)Type LEMA to bring up LEMA gui.
2)File -> New -> Project (Enter name)
3)File -> New -> Labeled Petri Net (Enter name, say one). After this,
you…
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I found verible searching for something to help me in my `make`-based build system. I'm looking for something that can function similarly to `gcc -M`.
Consider this file, `testcase.sv`:
```verilog…
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**Is your feature request related to a problem? Please describe.**
No directly related problem
**Describe the solution you'd like**
It would be great if highlighting support was available for the…
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[languages.yml](https://github.com/github-linguist/linguist/blob/cddf7476af4c95d1572956ffc5c0cb84f7e431c5/lib/linguist/languages.yml) in the GitHub linguist project has a good list of languages but I'…