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Hello,
I updated litex to retrieve last changes but I got an error with the parser.
Here is what I do :
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCA…
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**Describe the bug**
When running the sample.portability.cmsis_rtos_v2.timer_synchronization test on arc64 under qemu using picolibc, `z_init_static_threads` goes into an infinite loop in the second …
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Hi,
We are currently using latest HSS (0.99.33, release 2022.10) together with SoftConsole 2022.2 on an IcicleKit.
When programmed in Non Secure Boot Mode 1 (via SoftConsole), HSS boots successful…
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**Bug Description**
My aim was to replicate the steps taken on the following issues tab https://github.com/litex-hub/linux-on-litex-rocket/issues/29 to boot linux, more specifically `busybox`, onto a…
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Hi,
I have read issue #101 and #133. I could provide ssh access to my [Hifive Unmatched](https://www.sifive.com/boards/hifive-unmatched) and help to access some other RISC-V boards. If you have int…
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Hello, I have a problem with FT245PHYSynchronous fonctions from "litex.soc.cores.usb_fifo".
I connected my FT2232 chip to my Butterstick board (FPGA ECP5). Then I configured my inputs and outputs l…
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Just want to make a note that my Edimax USB wifi dongle that has been working for years is now not showing up after the latest Linux update.
> Linux:
> - Updated realtek WiFi drivers (Grzegorz Krz…
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您好:
编译香山后,在XSTop.dts中看到有串口地址定义:
L15: soc {
L1: serial@40600000 {
compatible = "xilinx,uartlite";
reg = ;
};
但是编译生成的xstop顶层并没有看到串口IO端口,只有一个jtag口。
有两个问题:…
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I have tested systems generated with Chipyard on an FPGA (VCU118). With Rocket and Boom I also get plausible results here with Dhrystone and Coremark. However, with CVA6, the results for Dhrystone are…
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Hello! I attempted to boot the prebuilt images without using the in-built simulator through using the following commands:
1.
```
litex_sim --with-ethernet --with-sdram --cpu-type vexriscv --no-co…