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Can it provide completions for common shells? TIA!
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Hello, VTR devs. This is Stefan Abi-Karam from Georgia Tech, and I am running into some simple parsing errors when it comes to using Odin II on some Verilog designs. The core issue is that Odin II see…
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This is not a bug, I would just like to discuss some of my findings.
I choose VexRiscv, since it seems to be the the most prominent FPGA implementation of RISC-V.
I did not synthesize VexRiscv mysel…
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[languages.yml](https://github.com/github-linguist/linguist/blob/cddf7476af4c95d1572956ffc5c0cb84f7e431c5/lib/linguist/languages.yml) in the GitHub linguist project has a good list of languages but I'…
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Hello, I am very interested in this project, but this FPGA project seems to be missing three dcp files, and the wcfg file cannot be opened. At the same time, what exactly do I need to do to run this p…
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Categories:
- BDD
- SystemVerilog / UVM
## Resources
1. [Pickles](https://www.picklesdoc.com/)
2. [BDD Addict](https://www.specsolutions.eu/news/bddaddict/)
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Dalance,
Not sure if there's interest, but a nice feature may be emitting SystemVerilog with back annotations of some sort.
While this would help humans who are performing verification to identify…
nblei updated
3 weeks ago
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I found verible searching for something to help me in my `make`-based build system. I'm looking for something that can function similarly to `gcc -M`.
Consider this file, `testcase.sv`:
```verilog…
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Hi,
having just compiled the latest `gtkwave3` I get the following error when loading an FST. The same FST loads fine in the Gtkwave I'm using via `apt install gtkwave` (v3.3.104).
```
GTKWave…
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Hello,
Are the CodeMap and the Outline Plug-Ins compatible one with another? It seems they are not ....
When I click inside of the Outline Plug-In, the cursor jumps to the CodeMap Panel, not to the…