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**Describe the bug**
In compatibility mode with VCS, using the slang compiler throws an error when a function name is used as a variable within the function's own scope. This behavior differs from VC…
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Hi,
I am trying to build the EL2 design for the Intel Cyclone 10 GX FPGA. This is using the free license within Quartus Prime Pro 21.2.
I am having issues with the `el2_param.vh `and `el2_pdef.vh`…
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你好:
麻烦问下我执行命令GscopeFind s 'xxx' ,去搜索某个函数xxx定义时,显示E259: not find 'xxx',请问这个咋解决呢?
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Hi all,
As far as I can see from the Chisel files the L1 D cache replacement policy is defined to be Random replacement. The Pseudo LRU policies are defined just for higher level caches and my att…
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我在使用rocket chip的 dev-difftest分支遇到如下error
(1) 准备工程:
https://github.com/OpenXiangShan/rocket-chip/tree/dev-difftest?tab=readme-ov-file
(2) 配置riscv-gcc
(3) 工程配置信息:
cp1@cp1:~/rocket-chip$ git branch…
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Hi!
After debugging for a long time why the LuaSnip plugin for Neovim doesn't load all my snippets, I think I've traced the issue to this (otherwise excellent!) library.
[The documentation for `…
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## Current Behavior
- Install debian package
- All the dashboard files PLUS config files are missing
## Steps to Reproduce
1. wget https://github.com/qdrant/qdrant/releases/download/v1.9.7/q…
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Hi @Alasdair ,
I noticed the Sail-to-SystemVerilog translator encounters difficulties with certain elements.
Specifically, it cannot translate `undefined`.
Below is a minimal Sail code example…
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This issue tracks the remaining subissues that must be fixed before UVM can be converted to C++. This first comment is updated periodically to summarize the most recent state.
**Note UVM is not ye…
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The ability to generate documentation from the veryl code is extremely useful.
It would also be helpful to have an option to remove or strip away the comments that are in the veryl code when gener…