-
### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
-
Hi! I am working on improving the VIA 6522 shift register implementation in VICE. I'm searching around for reverse engineering details regarding the exact timing of the timer, when it sets the timer 2…
-
Hello renode community,
I'm working on risc-v softcore with systemverilog and using a verilator simulator.
I want to integrate my work to renode for further experiments in network side.
I see i…
-
This issue appears to be independent of the Questa, Python or cocotb versions used.
I have a simple RTL simulation that uses cocotb running on Questa/Modelsim. On the simulation's conclusion I ca…
-
I noticed that when I run pytest with pipenv (which is fairly standard), the `run_filename` passed to the simulator is the parent directory of the Python in the virtual environment (e.g. `/home//.loca…
-
It would be nice if the simulator could be selected without setting an env var. Ideally, `cocotb_test.simulator.run` should be updated to accept a `simulator` argument that could select the simulator…
-
It seems to be verilog (`vlog`) only, I checked the documentation.
```
INFO cocotb:simulator.py:281 # vcom -mixedsvvh -incr -work some_lib /path/to/cocotb-test/tests/dff.vhdl
INFO cocot…
-
I'm playing around with the CIRCT integration tests. While doing so, I discovered some very weird behaviour related to buffers with more than one initial value.
I'm lowering the following to Veril…
-
I tried running the VHDL version of TinyALU and it did not work. The problem seems to be that nothing stimulates the clock in the VHDL design where it does in the Verilog.
I edited my Makefile like…
-
I'm trying to run a simulation of the example adder with a synthesized version of the design that includes a Verilog PDK library file and an SDF annotation file. CVC64 allows for SDF values to be ann…