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Hello,
Thanks for this great work, I appreciate the whole work. It is extremely beneficial.
Actually,I removed the constraint file of KC705 board, and I used the constraint file of VC707 board, and …
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Hello,
I updated litex to retrieve last changes but I got an error with the parser.
Here is what I do :
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCA…
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Hi,
I am attempting to perform phase coherent readout using a ZCU216, with a bitfile slightly modified from the q3diamond. My DAC and ADC modules are:
```
Board: ZCU216
Global clocks (MHz): tPr…
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**Bug Description**
My aim was to replicate the steps taken on the following issues tab https://github.com/litex-hub/linux-on-litex-rocket/issues/29 to boot linux, more specifically `busybox`, onto a…
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大佬你好，我把soDLA放在了Chipyard的generator目录下，并且将其中的sodla-wrapper目录拷贝到了generator中，并且针对依赖关系修改了Chipyard目录下的built.sbt文件，添加了如下所示的依赖：
```
lazy val soDLA = (project in file("generators/soDLA"))
.dependsOn(rocke…
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when I run install.sh, I got the following errors (all other steps are good). I am using the latest code as 02/19/2023
```
3. Main software...
mkdir: cannot create directory ‘build’: File exists
[…
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**Baseline:** 22/11
**Board:** polarfire icicle kit + QCA9880 wifi card
**ISSUE:**
DMA page allocation failures seen during bootup as CMA is OOM.
4.795291] swapper/0: page allo…
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您好：
编译香山后，在XSTop.dts中看到有串口地址定义：
L15: soc {
L1: serial@40600000 {
compatible = "xilinx,uartlite";
reg = ;
};
但是编译生成的xstop顶层并没有看到串口IO端口，只有一个jtag口。
有两个问题：…
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Hello, I have a problem with FT245PHYSynchronous fonctions from "litex.soc.cores.usb_fifo".
I connected my FT2232 chip to my Butterstick board (FPGA ECP5). Then I configured my inputs and outputs l…
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After flashing with using branch '9-support-for-jetson-orin-nano', GUI or display not working.
- minicom working and looks like it's flashed successfully.
- When using 'ACPI' on BIOS rather than '…