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https://github.com/efabless/caravel_mgmt_soc_litex/blob/43d0ce33d331ee73d9dcebe197c6ce4da5909ecc/verilog/rtl/mgmt_core.v#L1774C31-L1774C31
This like appears to connect the SPI master controller `Da…
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I'm trying to synthetize, implement and generate the bitstream for the NexysVideo board.
Firstly, I tried to do it manually following the instructions on the [user guide ](https://fraunhofer-ims.gi…
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The guys who made the Mojo v3 FPGA (awesome FPGA for beginners at a low cost around the Spartan 6 XC6SLX9) are coming out with two new boards:
* https://alchitry.com/collections/all/products/alchit…
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**Describe the bug**
A clear and concise description of what the bug is.
I'm looking for help with Litex Vexriscv on an Arty A7 35T. I'm unable to boot zephyr no matter what I try and I'm wonderin…
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I am using the ARM Cortex-M1 DesignStart FPGA for Xilinx (https://developer.arm.com/ip-products/designstart/fpga) reference design on a Digilent Arty A7 (https://store.digilentinc.com/arty) along with…
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Hi @tcal-x and @mithro ,
I'm getting the following error on uploading to the arty A7 board upon running the make load command. This hasn't happened before and I'm not sure of the reason why it has c…
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Dear charles,
How you recommend me to compile the updated code with
```
sbt "runMain naxriscv.Gen64"
```
like which branch to stay in spinal HDL and which branch to stay in main one ?
…
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Hello,
I've build the Ibex safe version for the Arty A7 100T board at 33MHz.
I've a correct result on /dev/ttyUSB1:
```
Ready to load firmware, hold BTN0 to ignore UART input.
```
I've build…
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Hi,
I am trying to follow the instructions but I get the following error: "qemu/opensbi/build/platform/generic/firmware/fw_payload.bin"
The folder qemu only contains the ./qemu/boot_qemu.sh. Am I…
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Hi @tcal-x and @mithro ,
I wanted to know if Litex just removes the L2 cache (ie, 0K) when we use a value of lower than 1024 bytes. Since, Ive noticed that when I put in a very low size like 64B , du…