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SDC files generated by OpenFPGA have buggy Verilog module hierarchy paths. I had a makeshift script to fixup the paths but it seems to have gotten worse, unless I'm doing things wrongly.
I run the …
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I tried implementing benchmarks with the pack array signal but failed at the yosys stage. Tell me have you tried with such RTL ? and how to solve
as far as i know yosys can't read RTL with pack si…
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Add the option for Pad 2 to remap their controls when the Analogue Pocket is docked. Pad 2 uses the default mappings currently.
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GB Kiss, was an IR communication method built into the cartridge of some Hudson developed gameboy games. Before it's availability on the gameboy color. It seems like this might be implementable using …
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It looks like OpenFPGA is already using Sphinx for it's documentation. There are a number of extensions that the SymbiFlow project and Antmicro have been working on to make Sphinx documentation for ha…
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In Pokémon Blue the color often changes briefly during battles (if sgb mode is enabled)
Is this a known problem?
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Hi,
When I used OpenFPGA, the tool required a configuration cell that has two outputs (one regular and the other inverted). However, the inverted port is left unconnected in the Verilog. If we can us…
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Are save states currently supported? If not, are there any plans to implement them?
I didn't see them specifically mentioned as unsupported in the README, but they aren't working for me on the Pock…
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Hello! I am using the latest version in master branch, and I am defining a new architecture. Now I am facing an Assertion Error I don't know how to tackle. It is hard to check what I am doing wrong in…
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Hi @tangxifan . I saw a custom CCFF design in 2019 FPL paper `(https://www.semanticscholar.org/paper/OpenFPGA%3A-An-Opensource-Framework-Enabling-Rapid-of-Tang-Giacomin/98004eb434646c323a11a050ead748a…
ghost updated
2 years ago