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I've noticed that there are at least two different approaches being used for encoding immediate values that exclude one or more LSBs in the ISA documentation. I think this multiplicity of methods coul…
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* [RISC-V toolchain on OSX](https://github.com/riscv/homebrew-riscv) rv64 by default and it doesn't work for picorv32
* to have rv32, please install [riscv-gcc](https://github.com/riscv/homebrew-risc…
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Hi,
everything is running smoothly until I try to do `make run-emulator-debug`. That results in the following:
```
running basedir/Makefile: make run-emulator-debug
make -C emulator/rv32_1sta…
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We're not the only group to have had the idea to use 2*XLEN bit operations. Zilsd uses LQ/SQ on RV64 and LD/SD on RV32 and will collide with LC/SC on Zcheri_purecap. Zacas defines AMOCAS.D on RV32 and…
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This issue serves as a tracker for remaining tasks to tag a 2.2 release candidate, and as a tracking mechanism for release testing once that is done.
## Blocking Tasks
- [x] Merge remaining timer…
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# Summary
|Build Failures|Additional Info|
|---|---|
|gcc-linux-rv32gcv-ilp32d-1e3312a25a7b34d6e3f549273e1674c7114e4408-multilib|Check logs|
|gcc-linux-rv32gcv_zve64d-ilp32d-1e3312a25a7b34d6e3f549273…
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Hi,
I am a bit confused by how zbpbo works, so I open this issue. Take `clz` as example,
> RV32: Replaced with CLZ in Zbpbo. RV64: Zpn
Does it mean, in rv32 we generate `clz` when the arch has…
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For the next spin enabling the [PCPI](https://github.com/cliffordwolf/picorv32#pico-co-processor-interface-pcpi) would be handy for extending the RV32 instruction set. I'm not sure if this is possibl…
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This issue will track the changes required to support the disassembly of RISC-V (www.riscv.org) instruction set. I will start with the support for RV64 first and then add the support for RV32 and comp…
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Zpn 0.9.5. did not require `smax64`.
Zbpbo requires it tho via `max` (spec says "RV32 and RV64" instead of "RV32 only").
There is no information about adding new instruction required for P-extension…