-
Hi, I am working on the physical ASIC implementation of this IP. I am integrating this IP into a new chip and I am having issue with the xilinx dual ports dual clock memories instantiated into dualmem…
-
Some visualization tools like the one in Model Sim allow you to get a trace on what conditions triggered the signal's change. How hard would it be to modify Verilator so that I could ask it what line(…
-
Coming from rodrigomelo9/FOSS-for-digital-HW-design#1
> Regards https://github.com/eine/vhdl-cfg, I thought about something similar between PyFPGA and others, such as edalize, hdlmake, tsfpga, and …
-
I just ran in to an issue with cocotb-test that needs to be addressed. I have a directory structure that looks something like this
root
+- rtl
| +- mod1.v
| +- mod2.v
…
-
This is a proposal for a new testers API, and supersedes issues #551 and #547. Nothing is currently set in stone, and feedback from the general Chisel community is desired. So please give it a read an…
-
The simulation results of syn_vivado.v synthesized by Vivado using iverilog and Vivado are inconsistent
For this, I tried on edaplayground.
[https://www.edaplayground.com/x/Fd7p](url)
You can use…
-
Dear Bruno,
my congratulations for squeezing a RV32I core into the Icestick !
I read your Verilog files with joy and I wish to share an idea on how to save a few more LUTs for more peripherals: …
-
While “legacy” integration is easily dismissed as a “detail”, in practice it is anything but. Getting this right gives designers an easy on-boarding path to a particular technology. Getting it wro…
-
Just found out about Qucs, did a fresh install on Ubuntu 20.04. The install was difficult, but I eventually was able to get most of it in except pdftex and repstopdf and some fonts. I was able to run …
-
Hello, I am very interested in this project, and I have met some problems in my study.
I have instantiated the `ddr3_x16_phy_cust` and `ddr3_rdcal` modules in your Arty S7-50 project, and programme…