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I am trying to develop a custom zynq board. Can anyone point to how I can generate this xci file that the zybo target uses?
https://github.com/litex-hub/litex-boards/blob/931f6667ac424d0bcd7dca0cf9…
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According to the schematic MDIO (MDC, MDIO) must be connected to PS_MIO052_501 and PS_MIO053_501 respectivelly.
In xci file the line 607 is wrong:
```
EMIO
```
and must be
```
MIO 52 .. 53
…
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Hi there!
I am running Vivado 2021.2 (64-bit) SW Build 3367213 on an Ubuntu 20.04 x86_64 PC and run into the following error message (extracted from vivado.log) when parsing the board_files provide…
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I'm trying to use OPTEE on my Zybo Z7 10 device, which is a zynq-7000 board. Since neither the Zybo nor the zynq7000 are a target of the optee build git, I have no choice but to clone the optee-os, op…
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Hello. Im trying to understand this issue.
I have a Zybo Z7-10 that i want to use with the PYNQ framework.
I successfully generated an image with the steps for agnostic board image but when i fla…
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Hey! I am porting cva6 into pynq-z2 (zynq7020), which has the same core as zybo-z7-20. I used BRAM as memory on fpga, so it's
easy to port. I followed the steps in Getting Started and everything we…
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I'm adding the PYNQ-Z2 to LiteX.
The process was pretty straight forward as I could base it on the Zybo Z7.
Unfortunately any CPU I use gets reset every 2-3 seconds.
By that I mean the behavior is …
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Hey folks,
I want to boot NuttX on Xilinx Zybo Z7-10 with Litex-Vexrisc-v core in it.
please tell me the procedure to this!.
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Hi,
I've setup the u-dma-buf to alloc 2 buffers on a Zybo-Z7-20 using petalinux and the device tree.
I've expanded the CMA to 128MB (cma: Reserved 128 MiB at 0x38000000)
My device tree configurat…
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Hey! I find this project [cva6-softcore-contest](https://github.com/ThalesGroup/cva6-softcore-contest) ported cva6 into zybo-z7-20. And I am working to port cva6 into pynq-z2 (zynq7020), which has the…