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Hi Eugene,
The RocketChip component of the riscv block design connects with the DDR component through an AXI4 interface. Within the DDR component, an AXI SmartConnect is used to connect the S00_AXI s…
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In the current implementation the `user` signal in `Axi4StreamBundle` is defined to be `dataWidth * userWidth`:
https://github.com/SpinalHDL/SpinalHDL/blob/ef0063da38424830a5b29f188e3887e2b043cb75/…
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axi_traffic_gen_0 file not found ? pls add it
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In the [TLMasterModel Trait](https://github.com/ucb-bar/dsptools/blob/2b6c009456914c3a4aa86b1a6bd7b870b128abfd/rocket/src/main/scala/tl/TestIP.scala#L50), there are [`tlWrite*`](https://github.com/ucb…
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# 问题描述
由于chisel导出的verilog没有数组,所以chisel导出的verilog代码可能无法直接用于difftest仿真。
例如,直接用verilog描述的信号为:
```verilog
Output [7:0] test [3:0];
```
使用chisel的描述语句为
```scala
val test = Vec(4, UInt(8.W))
```
…
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Hi, I think I may have found a bug in the PCIM interface model in sh_bfm.sv. The problematic logic (with lines omitted for clarity) is the following:
```verilog
if (sh_cl_rd_data.size() != 0…
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I have an interface:
```
------------ ---------
| Master |--req-->| Slave |
| |interp—>cmd_queue —> executor request
|
—>…
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The Rx buffer address location within the FlashMsg[x] struct (RxAddr64bit) is never set.
Value should be set to Destination Address (such as from `u32 XFsbl_Qspi32Copy(u32 SrcAddress, PTRSIZE DestA…
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__Objective:__
Add a `peek` functionality to the `queue_pkg`: returns the element at the front the queue. It does not deletes the element in the queue (contrary to the already existing `pop` command)…
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First off thank you for the hard work, this software you have created is really great! The biggest issue i've come across is problems with merge axis. The first issue I've had has been with response…