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FPGA-level simulation is brittle and run rarely. When we do need it, we _really_ need it so it's probably worth forcibly checking that it works in the CI for a small target running the smallest assemb…
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Hello,
I am currently working on utilizing the Axi DMA module through PYNQ. I have created an HLS Axi Lite module that allows me to control the Axi DMA IP module using wires. However, whenever I at…
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您好!
我在使用您提供的systolic array的时候,csim和csynth都没问题。但是在cosim的时候,会出现硬件计算结果和软件结果不同的问题,而且硬件结果都是0。请问有什么办法解决吗?~
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FIRRTL memories that do not go through the `--repl-seq-mem` path to replace them with blackboxes always produce a wrapper module around the memory. However, this can result in poorer performance for V…
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Hi,
Thanks for your constant support. I am able to run FPGA_CNN successfully.
Now, I want to classify some other data by using the same network structure as yours (CNN_MNIST).
What are the steps …
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when i'm running the examples:
./axidma_benchmark -t 0 -r 1 -b 1500 -s 1500-n 300
AXI DMA Benchmark Parameters:
Transmit Buffer Size: 0.00 MiB
Receivxilinx-vdma 40400000.dma: Channel ef3b9010 …
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Hello,
I'm looking to generate the Verilog/Vhdl of a VexRISCV multicore SMP processor but rework its IO buto AXI. I see it has been done for a single VexRISCV core:
https://github.com/SpinalHDL…
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I am trying to build FemtoRV petitbateu but it fails to build two different ways for two different toolchains.
When I build with yosys+nextpnr using command: `python3 -m litex_boards.targets.digile…
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Hi,
I am trying to get the pulpino implemented on a Zybo, I followed all the steps in the FPGA directory. everything seems to work correctly when I enter the command "make all", even the synthesis is…