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Currently, there are a number of personal annoyances with how Chisel/FIRRTL emits verbose randomization logic. This issues is a proposal to add an option to disable randomization logic generation (whi…
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The following code does not complete (at least not in 1 minute, so I call it infinite ;) )
```python
from nmigen import *
from nmigen.sim import *
class A(Elaboratable):
def elaborate(sel…
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Note: This is somewhat speculative; I haven't worked out all the details. Feedback is welcome.
In theory, there are three situations in which nodes that are implemented by the same hardware (e.g.: …
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Hello,
For some "`include" problems with Modelsim Starter, I could not get your flow working. Therefore, I decided to deploy a test project in Vivado.
I am trying to have the simple hello world…
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I used protect-lib mode for cosim.
TB is too complex, so vcs/xcelium could be used to handle that, while DUT is handled by verilator.
Unfortuantely, by default waveform dump is not enabled.
Wi…
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I am using following command to read the first address of the user box @ 250MHz.
`sudo ./pcimem /sys/bus/pci/devices/0000:3b:00.0/resource2 0x100000`
I get following error:
```
/sys/bus/pci/devi…
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Does verilator work with SystemC AMS, for example the proof-of-concept implementation from accellera.org (Coseda GmbH) ?
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As reported by @mcy in #524, you cannot run multiple concurrent verilator models.
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I'm trying to use the verilog files generated for the Sky130 SRAMs, but I encounter an error during RTL simulation. It seems the `mem` signal is used before it is declared (via this declaration: `reg …
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Hi Zach,
I would like to report what seems to be a bug in sv2v that may remain undetected using current open source tools, but which critically affects commercial simulators.
Let's consider the …