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Hi, thanks for this very useful software! I encountered a strange segmentation fault which I have narrowed down to this code:
```verilog
module interp1d_tb ();
reg clk;
initial begin
…
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When running the following test using testers2:
```scala
import chisel3._
import chisel3.tester.{ChiselUtestTester, testableClock, testableData}
import chiseltest.simulator.{VerilatorBackendAnnota…
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## Observed Behavior
When attempting to run rtl_sim under `ibex/dv/uvm/core_ibex` using questasim, the sim errors out before running, in particular during the `vendor/lowrisc_ip/dv/sv/common_ifs/clk_…
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Hello Noxim family ,
I came across strange problem simulating and evaluating routing algorithms.
XY routing receives more packets and more throughput while westfirst has much less , while base on pa…
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Why are two general-purpose register groups designed in darkriscv.v,
Not like one of the riscv specifications,
Is it to support multi-core?
reg [31:0] REG1 [0:31]; // general-purpose 32x3…
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Dear ghdl community, Im working with vcd files to compare simulation output with other simulators.
**The Problem**
Im using - a commercial graphical vcd compare solution that is not willing to ac…
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Hi,
I have been using BSC to compile some BSV code, and when modeling large memory structures, BSC does not emit sparse pragma in generated Verilog, I wonder if it possible to make it do it, as th…
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After reading the spec, I found a number of cases where our CPU was not complying with edge-cases of the MIPS I ISA.
We should write tests for these and include them in our test bench
I've categ…
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# Issie QOL upgrades
Below are a few things, mostly quality of life upgrades, that would make issie better. With this I'm not saying by any means that issie is bad, simply that these are some thing…
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Dear all,
I have a system verilog code for an adc. The simulation works fine on edaplaygrounds and am able to see outputs. To verify the design, I created a sample cocotb code and am new to it. How…