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This issue is also on Kasli-SOC as it shares most of the design.
The Kasli wiki mentions quite explicitly:
> 1 SMA to the clock recovery and clock distribution chip used as RTIO reference clock in…
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Hello,
I'd like to connect FPGA with the Silabs WF200 Wifi controller. From the IC spec, it basically requires SPI or SDIO bus interface. First of all, I want to try with SPI because it is simple, …
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[17:03:11:297] \ | /
[17:03:11:297] - RT - Thread Operating System
[17:03:11:303] / | \ 3.1.3 build Sep 7 2022
[17:03:11:309] 2006 - 2019 Copyright by rt-thread team
[17:03:11:309] Hel…
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The removal of `jtag_atlantic` seems to have been premature, given neither `nios2-terminal` not `litex_term` are able to connect to the JTAG UART synthesised by passing `--uart-name jtag_uart` when bu…
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仅仅是意见征集……
提醒一下,主编**可能**需要处理相当多的提案,所以请好好负起责任。
如果有的话也请把自己的优势简单讲一下,比如时间精力充足、有类似经验,当然单纯的热心也是很好的QAQ
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## 请下载最新的Nuclei Studio 2022.08 Windows版本
- 下载链接 https://nucleisys.com/download.php#tools
下载解压后,请[升级IDE的插件版本](https://www.rvmcu.com/nucleistudio-userguide-id-28.html#20)到最新版本
升级完毕后, 点击菜单栏 **RV…
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The riscduino is a great project, but after learning about it, I still have some confusion.
Is there a relevant FPGA test routine for the riscduino SOC?
There are some differences between the memo…
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Hi All
I would like to test the UART/SPI/I2C of Earl Grey. I noticed there are PMOD and FMC on the Nexys Video FPGA baord. Can I connect two nexys video FPGA through PMOD and test the UART/SPI/I2C wi…
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您好。我跑起来了。
就是串口通信 进了shell。。。
问题就是我不知道sdram模块是不是正常工作。。。rtthreader里面好像也没有检测sdram的函数
还有就是我的时钟是24m。我改了pll。运行在72m没有问题。
现在就是我想用里面的sdram模块。。。代码比较晦涩。。。所以我问一下
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