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Thanks for making this amazing library. I was just looking at the example on the playground and noticed that the wire rendering has some issues.
![image](https://github.com/tscircuit/schematic-vie…
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Need to generate the `pb_type.xml` and `model.xml` from the Verilog using v2x.
### Input Verilog
Things wrong with this verilog;
- [ ] Missing timing annotations.
- [ ] ???
```verilog
/*…
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Hi,
I've been spending a few days now on reading into TinyWireS, I2C protocols and standards.
After seeing the interesting discussions in different issues I do believe that TinyWireS offers suppor…
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### Minecraft Version
1.19.2
### Version
1.100.9
### Details
Basically: when `while true do print(os.pullEvent()) end` is running in a tab in a turtle's multishell, and the turtle disco…
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In the file "smartcitizen-kit-20/sam/src/SckAux.cpp", in the function `getReading()`, there is a line `if (auxWire.available()
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Once in a while the sketch hangs in the I2C_bus_OK() function right after the message [start_I2C_bus] Send Who Am I request to IMU shows up on the console. The code that causes the lock up is likly:
…
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## Steps to reproduce the issue
[minitest_bram_36.zip](https://github.com/YosysHQ/yosys/files/4298887/minitest_bram_36.zip)
Run `make bram.edif` to call yosys
Run `make bram_vivado.bit` to call…
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### Expected behavior
When calling qml.matrix on a qutrit qnode the resulting matrix should be (3^n x 3^n) (n is the number of wires).
For example when there are two wires the resulting matrix sh…
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Is there any way to express array of module (or generate syntax in verilog) in myhdl?
Array of module:
```
wire DFF_i[15:0];
wire DFF_o[15:0];
DFF d[15:0] (clk, DFF_i, DFF_o);
```
Gener…
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### Prompt
The flow needs proper way to handle the blackbox cells.
Verilog blackbox is used by the synthesis tool.
It tells the synthesis tool the purpose and width of the Input and Output.
In t…