-
I have to following error when trying to create project -
WARNING: [IP_Flow 19-5661] Bus Interface 'ACLK' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-11770] Clock i…
-
```
This is a fork of issue 99 where relevant aspects have previously been
discussed. Here some relevant comments.
---
#1 richard.eckart
I have added mapping files for NEGRA grammatical functions …
-
```
This is a fork of issue 99 where relevant aspects have previously been
discussed. Here some relevant comments.
---
#1 richard.eckart
I have added mapping files for NEGRA grammatical functions …
-
```
This is a fork of issue 99 where relevant aspects have previously been
discussed. Here some relevant comments.
---
#1 richard.eckart
I have added mapping files for NEGRA grammatical functions …
-
This is the HDL side of the discussion here: https://github.com/analogdevicesinc/libiio/issues/860
- _One 64-bit counter in axi-dmac, running on the sample clock. It would need to be readable from …
-
Upstream:
https://github.com/antonblanchard/vlsiffra
Hard-Dependencies:
yosys (but can use https://github.com/amaranth-lang/amaranth-yosys)
Soft-Dependencies:
- OpenROAD
- [ORFS](https://git…
-
I get this error when trying to build:
```
ERROR: An error occurred during the fetch of repository 'org_pcre_ftp':
Traceback (most recent call last):
File "XXX/_bazel_renau/3f7dad3b9f…
-
There seems to be a single massive GitHub Action which takes ~3 hours to build.
Really there should be a GitHub Action per Yosys plugin.
-
Modules have a ".domain" field [used primarily for reading back domains by name, usually aliased from `m.d`] and a ".domains" field [a list which is added to to define new clock domains]. I raised som…
-
Dear all,
what would be needed to add support for Xilinx Virtex 6 series of FPGAs?
I guess the reason that there is no support so far is mainly due to the fact that there was no demand. Or are t…