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Dear All,
Some recent change in Sail log has completely broken the [riscv-isac](https://github.com/riscv-software-src/riscv-isac) flow to find the coverage of arch-tests. Previously Sail log used to …
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or refactor common code into another crate to make it easier to port to other architectures
basically the only thing that needs to change to make this semihosting library work on other architecture…
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external/zlib (upstream: https://chromium.googlesource.com/chromium/src/third_party/zlib/) has SSSE3 and NEON intrinsics for adler32 among other things. Should RISC-V have similar changes?
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Now that the RISC-V port has been accepted upstream, it would be nice to backport it to all (active) branches. I have already prepared backports to jdk-18, jdk-17 and jdk-16, but they need to be veri…
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Hi!
I'm trying to implement RTT (real-time-transfer) feature for debug and tracing of code with OpenOCD.
Wiki of Segger said that
_RTT background memory accesses are performed either via via RIS…
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As said in external/VSRTL/core/vsrtl_wire.h, "all ports used in the wire's propagation function must be added to its sensitivity list". However, in src/processors/RISC-V/rv-registerfile.h, `wr_addr` w…
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This issue concerns the RISC-V version of the binary-to-graph decompiler in [examples/machine-code/graph](https://github.com/HOL-Theorem-Prover/HOL/tree/develop/examples/machine-code/graph).
When d…
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Does your cool libary support the [Sipeed Tang Nano 9K FPGA Development Board Gowin GW1NR-9 RISC-V HDMI (Tang Nano 9k)](https://www.amazon.com/-/de/dp/B0BCXYWV3T/ref=pd_vtp_h_pd_vtp_h_d_sccl_1/131-042…
Cr0a3 updated
4 months ago
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I'm going to implementing the support for the [Svadu](https://github.com/riscv/riscv-svadu). RISC-V Sail already has the [-d|--enable-dirty-update] flags. I wanted to get an opinion on if we should re…
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Some aarch64 machines (typically consumer machines that may need support for 32-bit apps) support 32-bit instructions, others (typically servers) don't.
This is hard to express in the archpolicies[…