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Hello,
I'm using the platform orangecrab and I've built a SoC using litex. I'm taking advantage of orangecrab's external SDRAM and thus I'm not using integrated main ram ([integrated_main_ram_size](h…
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Hello, I've been reading through the README and http://zipcpu.com/projects.html, but I haven't been able to find a list of supported FPGAs. (Sorry if I missed something obvious!)
Does ZipCPU have s…
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Origin
Name of Project : Trusted Firmware-A
Project Link: https://github.com/ARM-software/arm-trusted-firmware
Source Code:
https://github.com/ARM-software/arm-trusted-firmware/tree/master/pla…
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Hello,
Is it possible to move all the wiki pages into a 'docs' directory so that I can suggest edits?
https://stackoverflow.com/a/11481887
There is great content on this repository and I woul…
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Hi, big thanks for great project!
I'm trying to get linux with ethernet and sdcard on ac701 board.
My problems with this board was:
1) The board has low voltage on USB-UART CP2103GM. VIO port has …
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### Describe the issue you are experiencing
I have been trying to install HAOS on my Odroid N2 (not the plus) 4 gig SBC for some time now without success. I have tried multiple versions (9.3, 9.2, 8…
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I'm starting on these days to use the ICICLE Kit. In the latest README.md file is written "This repository supports Libero SoC V2021.2, which is available for download here". Unfortunately the V2021.…
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Hi all,
In order to demonstrate the LVGL cmsis-pack, I have created a porting for Corstone-300 running on Arm MPS3 development board that hosts a Cortex-M55 example design. Arm also provides a free…
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For simplicity, let's use the standalone generator:
```
$ ./gen.py arty.yml
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> < …
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I'm a little confused about the bootloader(soc/soc.srcs/sources_1/new/ocm.coe),Because it is the form of machine code,i do not know which hardware is booted.And I want to run the CoreMark or other pro…