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Zephyr RTOS is in the process of adding support for Physical Memory Protection (PMP), which was added to the RISC-V Privileged Architecture in version 1.10. VexRiscv is already supported by Zephyr, bu…
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Hi, can u plz write a tutorial about how to create a spinalhdl project from scratch?
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I went through the "Add a custom instruction to the CPU via the plugin system" (SimdAdd), but this instruction is combinational logic, I'm trying to add sequence logic instruction, eg, require multipl…
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I'm planing on refreshing this design based on experience with the current version.
These are the main features I'd personally like to cover:
- 2 Standard SYZYGY ports (each with: 32 I/O, 8 diff…
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We should extend this repository to support multicore configurations. To support this, there is a bunch of work that would need to be done, specially to VexRISCV.
@SpinalHDL / @Dolu1990 - Could you…
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Recently I tried running vexriscv SMP with 4 cores on arty a7 35t. But I was greeted with failed memtest. I did git bisect to narrow down which commit has broken 4 core implementation, and unfortunate…
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Hi,
How are the cachable address regions determined? I can't seem to find any setting or documentation / comments describing this. Does every address go to the cache, or is it everything except what'…
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# Description
I copy this code to my intellij:
```
class MySub extends Component {
val io = new Bundle{
val a = in UInt(8 bits)
val b = out UInt(8 bits)
}
io.b :=…
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HI guys, I am newbie to spinalHDL.
Usually, When I try to learn a new language, I prefer to try things handy, just like test anything of python in its shell.
I can run scala perfectly in this way b…
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I try to build system based on vexriscv, build I/D subsystem like below:
```
val core = new ClockingArea(coreDomain) {
val vexRiscVConfig = VexRiscvConfig(plugins = vexRiscVPlugins)
…