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hi all,
Currently i a m working on dma subsystem for pci express version 3.0 in tool of vivado 2016.3.
i was taken a 1 MB of bar size,when i was trying to accessing a entire memory location from dri…
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Hello everyone, I try to build zcu102 with adrv9025 but when running petalinux-build I have an error. I find many different ways but I still can not solve this bug.
Can you help me some idea or sugge…
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Hi,
I apologise in advance for the length of this post...
(We currently are developing on version 20.1 of the driver.)
We have extended the QDMA driver with network capabilities (similar to as …
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I am trying to use netv2-fpga as a develpment board. To use the board in Xilinx Vivado, I need to add the board to Vivado's available boards. This is normally done by adding the board files, including…
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This case doesn't seem to be described in the manual. It looks like `write_verilog` completely ignores `\EN` for anything other than non-transparent synchronous ports. Migen uses "latch address" for t…
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I am a bit confused about the functions to use to read and write from ONFI flash memory. Do I use the xnandps_onfi.c or the xnandps.c to read and write from ONFI flash memory? I see that xpandps is be…
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I am trying to build some of the simple examples but am getting a linker error:
```/usr/local/opencv4.4/lib/libopencv_flann.so: undefined reference to `std::__cxx11::basic_ostringstream::basic_ostr…
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XCI contains parameters of ipcore.
component.xml contains definitions of bus interfaces.
Import xci as a Unit instance.
* component.xml with pregenerated values usually stored in .srcs/sources_1…
Nic30 updated
3 years ago
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Tasks:
- [x] Ensure that RAMB36E1 can be placed and routed
- [x] ~~Add simulation model for RAMB18E1 and RAMB36E1~~ Xilinx Unisims now exist!
- [ ] Create test benches to verify pre- and post-pl…
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At least on Xilinx, an input-only pin have much wider IOStandard compatibility (you can have an LVDS_25 input on a VCCIO=3.3 bank but not an output).
Cleanup (make this less of a hack) https://github…