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### Version
Yosys 0.24+10 (git sha1 69cbef966, clang 10.0.0-4ubuntu1 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
When a SystemVerilog code contains an interface with …
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### Describe the bug
@bwuch
I have tested and followed run script second time failed #530. but it seems got another error see update in #530 and made this error.
I got error when I run command Ge…
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When generating a Verilog netlist using e/Teak you should expect a popup window (if you're using the GUI, if not try --help in command line) which asks you to select a technology library. e/Teak's tec…
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Hello @enjoy-digital,
I want to simulate the bare metal demo application on RISC-V cv32e41p and I had this bug of no prompt response.
However, it works fine with the cv32e40p core.
(The litex …
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Hi, very nice work and clean realisation.
But when I reproduce the results from the paper, I have some problems. Especially when reproducing VCD in using greedy search as decoding strategy.
Under th…
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We had an incident at a customer side today with the following piece of code:
``` python
from pyVmomi import vim
filter_spec = vim.TaskFilterSpec(alarm=None, scheduledTask=None, state=["runni…
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I tried to decrypt a My Passport with the Initio INIC-1607E chip but it keeps asking for a password. I verified in the SA of the drive that no password is set.
Let me know if you want any of the SA…
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I am in mint and get things like this,
![image](https://github.com/yne/vcd/assets/2415206/169f5b5d-2f3e-4a59-994d-65bc17cffda6)
So it is not ideal
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On Ariane, the CPU ceases to respond to interrupts after a while, and I am testing the hypothesis that it is the simultaneous arrival of multiple interrupts that is causing the problem. I attach a wav…
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The meaning of time flow between different kinds of simulation targets has diverged, and even within a given target there are some inconsistencies (e.g., some delays are in seconds, some nanoseconds, …