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[Taiga](https://gitlab.com/sfu-rcl/Taiga) is a 32-bit RISC-V processor designed for running Linux and SMP type things on FPGAs. Taiga is licensed under the [Apache License, Version 2.0](https://www.ap…
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**Description**
In simulations where an iteration of the top modules is performed with vpi_iterate/vpi_scan the memory usage increases every time a new iterator is created and consumed. If too many …
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I am getting trouble implementing shift behaviours as available in Verilog.
In SpinalHDL there is `>>`, `` and `|
saahm updated
4 years ago
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**Description**
In simulations where events are scheduled by a VPI plugin using vpi_register_cb, even if no wave files are specified, the memory usage increases every time a new callback is registere…
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I'm currently having a weird issue with cocotb 1.4 and verilator 4.100
I'm verifying an asynchronous FIFO design and have a basic 'manual, section which works perfectly, where I test reads and writ…
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This is probably related to issue #160 -- might even be moved into that issue if it turns out to be directly related.
I initialize a memory directly via a function in a Tools class -- pretty much as …
saahm updated
4 years ago
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Hey,
I'm trying to implement a Register File for a RISC-V, yet the design generated does not equal the described design in SpinalHDL:
```scala
class RV32RegisterFile(addressWidth : Int, dataWid…
saahm updated
4 years ago
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**Description**
When using vpi_set_value on a VHDL enum (without encoding hints), apparently no effects are produced (no writes), reading from a VHDL enum type returns a null. An implicit sequential…
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At this line, should this be a change directory to ```SpinalTemplateSbt``` instead of ```SpinalBaseProject```?
https://github.com/SpinalHDL/SpinalDoc-RTD/blame/master/source/SpinalHDL/Getting%20Start…
tulth updated
4 years ago
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Hi:
Add `tags.generateAsBlackBox()` to (https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/ip/DataCache.scala#L398)
and then run `sbt "runMain vexriscv.demo.GenFull"`
and th…