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**Name:** Bluespec Systemverilog
**URL:** https://github.com/B-Lang-org/bsc
bsv is one of the languages used for hardware development,
Some sample error messages are
```
% bsc -verilog u…
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我是做FPGA开发的工作者，初次体验了最新的这个插件，想给出如下建议以及觉得不错的地方：望采纳
1.我觉得那个architecture功能做的不错 可以看到代码的层次结构图，在开发FPGA的时候不用来回的切换vivado界面，比较不错。
2.代码的颜色高亮有点点问题，关键字和变量常量的显示都是蓝色--这个不太具有突出性，我查看的是你里面的fft代码---可以参照插件 Verilog-HDL/S…
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[languages.yml](https://github.com/github-linguist/linguist/blob/cddf7476af4c95d1572956ffc5c0cb84f7e431c5/lib/linguist/languages.yml) in the GitHub linguist project has a good list of languages but I'…
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I've noticed that ppx_deriving_yojson has a far more comprehensive testsuite than the other plugins. I think it might be useful if all the various plugin authors contributed to a shared testsuite tha…
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> Note: I'm not sure if this should be an issue or a discussion. I think you can convert between them. Feel free!
I'd like to make two small suggestions to the rule syntax. I realize this is a topi…
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This first comment just describes the issue(s). Follow-up comments
discuss possible solutions.
Currently the Sail model writes out a log file in ASCII format. Issues:
* Logs can become very lar…
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This is with a custom `maxOtherSize` (I set it to 10% instead of 5%). Maybe this is the cause?
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Given this BSV code:
```bsv
package Foo;
import Vector::*;
module helloWorld#(Vector#(2, Reg#(UInt#(32))) v, Reg#(Bit#(64)) idx)(Empty);
rule hello_world;
v[idx]
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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R language isn't included in markdown-gfm-recognized-languages
## Expected Behavior
The list in `markdown-gfm-recognized-languages` includes the item "R"
## Actual Behavior
It does not exi…