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### Description
I see that [bluepills cpu definitions](https://github.com/renode/renode/blob/master/platforms/cpus/stm32f103.repl) don't include CAN like [STM32F4 does](https://github.com/renode/re…
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1. I use this command to generate a Verilog project with wishbone bus: `python3 -m litex_boards.targets.digilent_basys3 --integrated-rom-init=test.bin --integrated-main-ram-size=0x2000 --build`, then …
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A chapter is to be created on how synchronization points between a Network FMU and a Bus Simulation can be recognized in advance within the Network FMU. This chapter shall be part of the FMI LS BUS Im…
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Add functionality to update values in the data collection objects for buses and branches in dynamic simulation. These values can then be queried and extracted by other applications.
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### Feature Checklist
- [X] Searched the [issues page](https://github.com/e2nIEE/pandapower/issues) for similar reports
- [X] Read the relevant sections of the [documentation](https://pandapower…
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- JLCPCB Constraints: https://jlcpcb.com/capabilities/pcb-capabilities
- [ ] Drill Diameter Min/Max
- [ ] Pad Hole-to-Hole Spacing
- [ ] Edit this issue to add more!
Video explanation: https…
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A chapter is to be created on strategies of decoupling Fixed and Variable Step Size FMUs within the same simulation network.
This chapter shall be part of the FMI LS BUS Implementers' Guide and is r…
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### Describe the feature
Create an embeddable class for all parts (Export Bus, Level Emitter, Interface, addons) that can automatically start and own a crafting job, and an associated management GU…
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### Feature Description
I am currently trying to magically speed up the simulation of [dmgcpu](https://github.com/emu-russia/dmgcpu) by checking if I can get yosys to optimize out all uses of high-im…
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The RocketTile has servial connections with the context:
```
connectMasterPorts(domain, context)
connectSlavePorts(domain, context)
connectInterrupts(domain, context)
connectPRC…