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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/)
### Feature…
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@ccelio I'd like to update this document to Chisel3 it seems to be the most findable chisel style guide out there. I'd be happy to submit a PR to this repo or could fork to a chisel organization. Do y…
chick updated
5 years ago
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
```scala
import chisel3.experimental.hierarchy._
implicit val mg = new chisel3.internal.Macro…
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Hello Community,
My team is planing to tapout a chipyard based design, and we have a different Clock Scheme from the default chipyard design:
…
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This has been talked about on and off for quite a while now, but some of the utilities in rocket-chip, like the async FIFOs, are quite general and would be good candidates for inclusion in a chisel st…
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If you use `git config --global url.'https://github.com/'.insteadOf 'git@github.com:`, you'll get the following on `wit update` with `v0.11.1` and `master`
```
[WARNING] Package 'chisel3' wants a di…
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When running yosys -p "read_verilog -sv generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.sv"
on my newly generated System Verilog code, after finally extending Yosys for the new syntax…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
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Some big apps get random firrtl errors, so it seems the best way to bypass this is to use protobuf inbetween chisel and firrtl to avoid the firrtl parser. This should also speed up compile times.
…