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Currently we need user-provided filters to choose which instructions or sets should (not) be processed by Seal5. See:
```yaml
---
filter:
sets:
drop: [RISCVBase, RISCVEncoding, Zicsr, Zif…
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Signed registers declared in the CoreDSL2 model are converted to unsigned in ETISS.
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The following code does not work with the CoreDSL2 frontend and the ETISS backend:
```
VXSAT_CSS[0] = 0b1;
```
As a workaround `VXSAT_CSR = VXSAT_CSR | 0b1;` works just fine.
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Hello,
the following coredsl2 code:
```
void foo(){
unsigned a = 3;
unsigned b = 1;
unsigned x = 0, y=0;
unsigned z = x::y[a:b];
}
```
is producing:
```c++
static inline void foo…
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I realized in the below operation wrong return value `Z` is generated during the summation of X and Y:
```
unsigned foo(unsigned X, unsigned Y){
unsigned Z = X + Y;
return Z;
}
```
I be…
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When trying to enable implementation specific lines in the Interrupt enable registers, bits above 12 are ignored by CSR Write instructions.
https://github.com/riscv/riscv-isa-manual/releases/download…
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I was following the [coredsl2 manual ](https://github.com/Minres/CoreDSL/wiki/Expressions#concatenation) and I am having trouble using the concatenation operator during etiss code generation phase.
…