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Hi @lcgamboa !
Just discovered your amazing and impressive simulator, that's very cool!
I have a question, is it cycle-accurate? Meaning that one can (or could) run at precisely 8 MHz and the output…
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#### Found a new location? [Use this form here](https://github.com/jeanropke/RDR2CollectorsMap/issues/182)
* What day cycle it is? [Cycle 1]
* Coordinates or a clear image of the location [The neare…
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The ARM7TDMI emulation isn't counting cycles accurately.
Need to pass most of the mgba-suite timing test
![image](https://user-images.githubusercontent.com/2903914/82161185-46044e80-98a3-11ea-8e4d…
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Find a way to make the CPU match the cycle count of TIS-100.
Problems with the current design:
1. Certain port instructions require 2 cycles because arithmetic instructions can only read registers.
…
jdryg updated
9 years ago
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Is it possible to perform cycle accurate simulation using the inbuilt simulator in migen?
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With ISS as one abstraction level option in Wireguard-FPGA [sim TB](https://github.com/chili-chips-ba/wireguard-fpga?tab=readme-ov-file#simulation-test-bench), we are looking for it to be timing-aware…
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* You can use SYSCLK to get a 32-bit timer count for cycles from the system clock, so you don't have to worry about overflows
* You can use the AWU IRQ Handler to get interrupts when the AWU triggers…
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I’m encountering challenges with fine-tuning XTTS for Moroccan Darija despite having a high-quality extensive dataset.
Dataset: 1,000 hours of Moroccan Darija audio, segmented into 1–5 second clips, …
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I’d like to request a new feature to be added to the tool. Specifically, I'm looking for a "Fix Battery" option that forces iOS to resynchronize and retrieve fresh battery health data from the Battery…
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I'm having issues using the csv_compare method to verify that two traces are matching. I'm using Spike as a golden reference. However, Spike is instruction-accurate, while the RTL model is cycle-accur…