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Starting this issue as a tracker where we can keep our ideas and progress.
**Current conclusions**
Yosys can be extremely quick and could be added as a backend for netlist builds. These netlists m…
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**Description**
When using the GHDL plugin to yosys, and probably more generally, attributes are not attached to instantiations. This causes (for example) yosys to optimise away instantiated blocks …
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The [Yosys GHDL plugin](https://github.com/ghdl/ghdl-yosys-plugin) is still listed as experimental but is already very useful. For formal verification GHDL's support for PSL seems more extensive than …
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On Ubuntu:
Yosys:
```
sudo apt-get install build-essential clang bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev li…
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In order to use VHDL with the yosys flows, we need ghdl and the ghdl yosys plugin to be part of the environment.
https://github.com/ghdl/ghdl-yosys-plugin
https://github.com/ghdl/ghdl.git
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Given YosysHQ/fpga-toolchain will soon be deprecated, having this repo support GHDL and ghdl-yosys-plugin will make it a lot easier for those who use VHDL to transition over.
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Hi there, not an issue more of a question.
Currently for formal verification SymbiYosys and Verilog/SystemVerilog are used. As documented [here](https://spinalhdl.github.io/SpinalDoc-RTD/master/Spi…
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**Describe the bug**
When I click to the Schematic viewer button, the out put is :
2024-03-11 12:53:09.710 [error] Yosys failed.
2024-03-11 12:53:09.716 [info] yowasp-yosys -p "read_verilog -sv …
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First I cannot build ghdl locally, so I use the latest release from [fpga-tool-chain](https://github.com/YosysHQ/fpga-toolchain).
And I am able to run binary `ghdl`, but when I try to build ghdl plug…
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**Description**
I am hitting this assertion and erroring out
https://github.com/YosysHQ/yosys/blob/41b34a19353dbbe00aa08f3561e25e0bfa4c84d2/kernel/mem.cc#L473C5-L473C33
```
if ((port.transparency_…