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```
write_cfgmem -format bin -size 32 -interface SPIx4 -loadbit "up 0x00000000 $bitfile" -file "$binfile"
```
As per this command, we can see the quad mode is introduced during conversion from b…
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Dear all,
I am developing the Packet_Processing project , that DPI the RTP Video Stream. I need to capture the Value of Timestamp, SSRC … to PC Host via USB_UART. Due to NetFPGA 1G CML is not s…
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hi, I found your repos contains [segbits_riob18.db;](https://github.com/kazkojima/db-workspace-for-kintex7/blob/cada09e183052525b5382757e31121bbbedffc0a/segbits_riob18.db) The fuzzers in prjxray can't…
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In Package2017_2_1.tcl on line 728 (commit 81b232aacc3faff6c41964024de181b81e4493aa) the list of supported families is defined as follows:
set_property supported_families { \
…
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Hi @jrrk2 and @unbtorsten,
did you encounter this error while fuzzing that the mentioned fuzzer generates empty verilog files,
because it cannot find `prjxray/database/kintex7/xc7k160t/tilegrid.json…
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Hi. I succses used this project with a little bit modifications for 10G ethernet kintex7. Now I want to apply ip ten_gig_pcs_pma_0.xci for ultrascale. The specification PG068 states that I should use…
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I have tried a design on kintex7 using nysa_sata , but for now , only completed the oob , I think there maybe
bugs in the rtl code , some in the oob module have been corrected , others haven't been…
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I have Xilinx Kintex XC7K325 board and ECP5 color light 75b board and openFPGALoader works fine with ft2232 cable. However, I am not able to load the bitstream using CH347. I tried both Xilinx and Lat…
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Hi,
I struggled with this strange issue for a couple of days and finally found out that,
for some weird reason, configuration failed (DONE pin on the FPGA not coming high)
when I tried to load a L…
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at the merge of the high performance banks https://github.com/f4pga/prjxray/actions/runs/3534822169
a number of lines from the fuzzer 034b-cmt-mmcm-pips disappeared from these database files:
```d…