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https://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty
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i.e. the routing pics and the machxo fpgas.
should these be auto-updated?
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Would be great to support key programming for the Lattice ECP5 (key is OTP and non-volatile).
In [ECP5 FPGA-TN-02202-1.7 ](https://www.latticesemi.com/view_document?document_id=39450) are some info…
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Hi, I'm trying to synthesize this project and running into some errors.
I have very little experience with FPGAs so I'm sure I'm doing something wrong. I'm willing to learn though. My goal is to cr…
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I have had great success in using `openFPGALoader` to burn a program to RAM on my Lattice MachXO2 board. However, when I try to burn to flash, it fails:
```
# openFPGALoader --busdev-num 000:005 --f…
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Hello,
i've searched the Aliexpress for absolute cheapest FPGA boards and i've found very cheap devices that i think might be worth supporting:
- Noname chinese bargain FPGAs
- https://hackaday…
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Hello,
Nice project, one question though: why don't you use Edge Plating instead of pins?
https://www.google.de/search?q=edge+plating&client=ms-opera-mobile&channel=new&espv=1&prmd=isvn&sxsrf=ALeKk0…
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Taj source napravljen je za FleaFPGA pločicu
http://www.fleasystems.com/fleaFPGA_Uno.html
koja ima nešto durgačiji lattice čip ali je isto
razvojno okruženje diamond pa source prije
stavljanja na g…
emard updated
8 years ago
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For custom application only. This would provide low cost alternative. Currently this is experimental. Only supports PoE display using 16x96 RGB with MBI5124 panels.
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#183 put in an adabot patch for removing bad-whitespace from pylint invocations, but I don't think that this causes the patch to actually be applied.