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Hi Viktor, did you porting this block design on MicroBlaze V ? I'm very curious about this.
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When integrating Microblaze with UberDDR3, Vitis throws "Instruction overrun" error after configuring the FPGA. Ideally, the Microblaze fires up and waits at the first breakpoint at start of the progr…
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Is there any undocumented flow for embedded FW development using a MicroBlaze inside the CL, with the AWS-FPGA HDK?
In my on-premise environment, using u200 card, and following the instructions fro…
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Xilinx/AMD FPGAs support Microblaze soft CPU (IP core).
What about support it's assembly/elf files?
Processor reference guide with ISA & opcodes can be found [here](https://docs.xilinx.com/v/u/e…
AJIOB updated
7 months ago
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**Is this request related to a particular hardware platform, SoC, board? Please describe.**
Hello
Is threadX supported on Xilinx Microblaze soft processor which use RISC-V 32 bit? I see there is s…
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## Environment
```sh
Wed 29 Mar 09:33:02 CEST 2023
radare2 5.8.5 30445 @ linux-x86-64 git.5.7.8-1255-gf5749b7732
commit: f5749b7732dbeb561a59b73f24b6d793bbba20c6 build: 2023-03-29__09:28:30
Lin…
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If I'm not mistaken, when I have multiple 10 GbE devices in a model (SNAP), the MicroBlaze controller takes control of the first one alphabetically. This is both non-intuitive and undocumented, as far…
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I have posted my problem in , but I realise that it seems to be a different issue, as in the implemented design, the MDM is not connected to anything:
![schematic](https://github.com/aws/aws-fpga/a…
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I'm seeing this error when building greenlet using buildroot's ci [here](http://autobuild.buildroot.net/results/be7/be709462bbab54e4f405302d54d157218f867939/build-end.log).
```
greenlet needs to be …
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When testing with a microblaze core that has a AXI timer, freertos fails to get tick interrupts with the hello world example and the example simply hangs on the first vTaskDelay.
![image](https://…
tlf30 updated
2 months ago