-
While running it as
> ./litex-boards/litex_boards/targets/sipeed_tang_nano_20k.py --toolchain=apicula --build
getting this error
```
INFO:SoC:Initializing ROM rom with contents (Size: 0x64e…
-
Hello, I don't know if I should post the Issue here or on the LiteX repository, after running the following command I get this terminal output:
```
python3 -m litex_boards.targets.radiona_ulx3s --…
-
### Discussed in https://github.com/konosubakonoakua/blog/discussions/7
Originally posted by **konosubakonoakua** March 12, 2024
# zynq
## Manual
- [Embedded-Design-Tutorials](https://xili…
-
I run the mass-storage.py example and then measured the performance using the linux dd command.
Something like this:
`dd if={mounted_device_path e.g. /dev/sdf} of=/dev/null bs=512 count=100000`
T…
-
Hello,
I'm building a softcore based on Briey.
I've the AxiCrossbar without Sdram and on the APB3Bridge 1 Timer, 1 UartCtrl, 1 Gpio.
On the APB3 I would like to add a custom Ctrl to transfer in a…
-
# FPGA Development with wujian100 SoC - Part Nine: Working on Bugs - shieldjy
FPGA Development with wujian100 SoC - Part Nine: Working on Bugs
[https://shieldjy.github.io/post/FPGA-Development-with-…
-
Hello,
### Issue Description:
There are a few critical warnings which I believe could be solved relatively easily.
A lot of the critical warnings present on the vivado.log file are related to…
-
Theres both the xilinx Zynq soc with it's integrated FPGA (usually referred to as "the" rio FPGA), and the Lattice MachXO2-640. Neither of these have easy qemu support but i found https://www.xilinx.c…
-
Hi, when I ran the flow I got the error message in both case.
I have checked the software requirements and version, then I used "$make check" to ensure that I don't miss any requirements.
Here are …
-
Then in case of an overdrive the buffer will fail, not the FPGA.
Similar thing should be done on Kasli and Kasli SoC as well IMO.