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Just like the VHDL or Verilog Generation, does SpinalHDL generate SystemVerilog codes and needs some basic info about using the verification environment in SpinalHDL?
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I notice that `DBusSimplePlugin`'s Wishbone bridge forces all reads to appear to be 32-bits wide:
https://github.com/SpinalHDL/VexRiscv/blob/0af9894e698288d65f6127c4a2806986dbabf09c/src/main/scala/…
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Hello!
I’ve noticed that the floating-point operation core/plugin in VexRiscv, especially the commonly used floating-point adder and multiplier, seems quite stable now. Are there any plans to inte…
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It would be good to have examples of SpinalHDL examples on the fomu-workshop.
The Fomu uses VexRiscv internally (see https://github.com/SpinalHDL/VexRiscv). It would be awesome to be able to use a …
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As a way to scale up SpinalHDL we are looking at :
- Companies sponsorship as a way to provide funding to the SpinalHDL maintenance
- Open a https://opencollective.com/ or https://liberapay.com/ …
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Hello!
Did some files or dirs dont commit?
https://github.com/SpinalHDL/SpinalHDL/blob/2a34c667e8b72568a8b6c25f4a926863b8e068ed/sim/src/test/scala/spinal/sim/TestVCS.scala#L21
when run TestVCS1…
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While we don't know about good open-source linters for VHDL and SpinalHDL, **(System)Verilog** has got at least three: **Verilator**, **Verible**, **Slang**. Check [this](https://github.com/chili-chip…
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Although SpinalHDL `Vec`s work well for interfacing between SpinalHDL components, they produce a bunch of named ports in Verilog modules, which can make it really tedious to interoperate with existing…
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I've tested xilinx IPs like multiplier, complex multiplier, divider and FFT in spinal-sim using XSim, most of them work just fine.
But complex multiplier and FFT seems not working properly. I change…
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In SpinalSim we now have the capability to interact with buses like AXI to read bits from the design. My design currently exposes some SpinalHDL `Bundle`, `Union` and `SpinalEnum` over AXI and the si…