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1.刚开始是build.sbt能Build Module,但是运行top.scala会报错
Error:scalac: Error: org.jetbrains.jps.incremental.scala.remote.ServerException
java.lang.reflect.InvocationTargetException
at sun.reflect.NativeCon…
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#### Description
When running a simulation with a large time duration (~500k seconds), the waveform generated using the `.withFstWave` option cannot be opened in GTKWave. Attempting to load the `.f…
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It would be good to have examples of SpinalHDL examples on the fomu-workshop.
The Fomu uses VexRiscv internally (see https://github.com/SpinalHDL/VexRiscv). It would be awesome to be able to use a …
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As the doc claimed,
```
AFix.S(2 exp, -2 exp) can represent: -2.0, -1.75, -1.5, -1.25, -1, -0.75, -0.5, -0.25, 0, 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75
```
However, the following codes fails to comp…
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Just like the VHDL or Verilog Generation, does SpinalHDL generate SystemVerilog codes and needs some basic info about using the verification environment in SpinalHDL?
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As a way to scale up SpinalHDL we are looking at :
- Companies sponsorship as a way to provide funding to the SpinalHDL maintenance
- Open a https://opencollective.com/ or https://liberapay.com/ …
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Hello!
I’ve noticed that the floating-point operation core/plugin in VexRiscv, especially the commonly used floating-point adder and multiplier, seems quite stable now. Are there any plans to inte…
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### Version
Yosys 0.29+21 (git sha1 147cceb51, clang 10.0.0-4ubuntu1 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
This is a really basic unit test to valid…
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The SpinalHDL/docker now contains all elaboration and formal verification tools.
If this project can base on that with Gtk online support then a lot of man power can be saved.
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Recently, I am dealing with [ibex-demo-system](https://github.com/lowRISC/ibex-demo-system). There are many cores and I find it hard searching for RTL in each .core file because they loop deeper in ve…