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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched the [documentation](https://docs.fires.im/en/stable/)
### Feature …
cmx-Y updated
2 weeks ago
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What is the difference between the two from an architectural SOC viewpoint? And how can I find the memory map for what peripherals are created for each file? Also how to
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Hello,
I have my top module in verilog. I included it in RoccBlackBox.v which is in `rocket_chip/src/main/resources/vsrc/`. I also changed the configuration file Configs.scala in `rocket_chip/src/m…
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Hello,
I am totally new to the RISC-V domain. I considering implementing Rocket Chip on FPGA, and I found out that this is doable using SiFive Freedom.
However, it is stated that the supported b…
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Bumping to Xilinx Vivado2023.2 in our current container environment is failing with a couple of errors.
**Desktop:**
- OS: ESP centos7-full docker image
- CAD tools versions: Xilinx Vivado 2023…
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It is in the README.md that the `This flow requires Vivado 2016.4. Newer versions are known to fail.`
but I was still trying the build on vc707 with latest vivado and the bellow patch was able to mak…
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See:
- **Controller:** https://www.xilinx.com/support/documentation/ip_documentation/axi_emc/v3_0/pg100-axi-emc.pdf
- **Driver:** https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_services/xilfl…
stv0g updated
4 years ago
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@mcd500 Hello, first of all, thanks for adding support for the no-PCIe version on vc707. I generate Verilog and bitstreams using the following command successfully.
```bash
make -j16 CONFIG=DevKitU5…
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I can't install the Bluespec compiler, because the version is too old. I used [BSC](https://github.com/B-Lang-org/bsc) instead of. However, i can't find the ddr3 ip .v. Because you have the two steps.…
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Hi,
I wanted to experiment with BlackParrot a bit. First, I test using the Xilinx VC707 board the bitstream didn't work, then I simply use the litex_sim with cpu-type = blackparrot, but it didn't w…