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VILLASframework
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fpga-hardware
GNU General Public License v3.0
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Make project REUSE compliant
#20
stv0g
opened
1 year ago
0
Update Steffens mail address
#19
stv0g
closed
1 year ago
0
Reduce size of PCIE BAR0 to 1M to avoid mapping issues when detecting the PCIe device post-bootup
#15
stv0g
opened
3 years ago
0
Create overview table over different Aurora IP parameters for RTDS, OPAL-RT & FPGA partners
#14
stv0g
opened
3 years ago
0
Xilinx-Ubuntu VM unreachable
#13
stv0g
closed
1 year ago
1
Add constraints for faster technologies SFP/FMC module
#12
stv0g
closed
1 year ago
2
Complete location constraints for Trenz FMC/SFP module
#11
stv0g
closed
1 year ago
2
Testing Aurora IP core with ZCU106 board
#10
stv0g
opened
4 years ago
0
Dev - [closed]
#18
stv0g
closed
1 year ago
1
Add AXI EMC controller to VC707 design for flashing bitstream into configuration memory via PCIe
#9
stv0g
opened
4 years ago
4
Irregular reads from DMA
#8
stv0g
opened
4 years ago
2
WIP: Add tlast and tready signals to aurora_axis - [closed]
#17
stv0g
closed
1 year ago
1
WIP: New Makefile - [closed]
#16
stv0g
closed
1 year ago
11
Implement AXI_S_WSTRB logic
#7
stv0g
closed
1 year ago
2
Add intra-frame delay timer and respective status register
#6
stv0g
opened
4 years ago
0
Upgrade hw_server on Ernie to Vivado 2019.1
#5
stv0g
closed
1 year ago
1
Move aurora-rtds project into `ips` folder
#4
stv0g
closed
1 year ago
2
Add Verilog code to aurora-rtds IP to generate sequence numberes
#3
stv0g
closed
1 year ago
4
Include IP core version into IP TCL scripts and emit warning if version mismatch
#2
stv0g
opened
4 years ago
0
Licensing issue with Vivado 2019.1
#1
stv0g
closed
1 year ago
3