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Slowly making replacements for the Qucs Verilog-A Library devices.
1) Modded VCR.sch to get rid of divide by zero if Vin=0 volts. What actual VCR is chosen is TBD.
2) A new mod-amp was created usi…
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I was trying to compile the attached basic Verilog-A module (vco.va) and OpenVAF crashed. The crash log is also attached. I added a .txt extension to be able to attach the files.
For what it's wort…
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Adding a tool that can format Verilog helps us keeping the code clean and tidy.
This should be able to run in CI, and from Makefile locally.
[Verible](https://github.com/chipsalliance/verible) se…
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The VPR test `test_odd_even_routing` (as shown below) has consistently failed in CI (U: C++ Unit Tests) since https://github.com/verilog-to-routing/vtr-verilog-to-routing/commit/2b6a935494363f8be1a83a…
ueqri updated
2 weeks ago
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The intra cluster placement code used by the ClusterLegalizer is a bit dis-organized and uses C-style semantics which make it hard to read, use more memory, and may even make it slower. The following …
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**Describe the bug**
Actually I am not quite sure if it is a bug or a feature. The plugin always insert a "\t" in front of the first signal connection when using the "module instantiation" provided b…
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If you try to parse an IPXACT file with a Verilog number 'h4834 (which is legal) it will fail.
May be use the Verilog regex parser?
const char VERILOG_PARSER_REGEX[] = "\\s*([0-9]*)'([hbdo])([0-…
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I'm using Arch Linux's `vim-runtime 9.1.0707-1` package and noticed that Verilog syntax highlighting stopped working. I found that editing this line:
https://github.com/vim/vim/blob/f21d28a5c72987d…
ZakSN updated
3 weeks ago
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Hi,
I'm trying to check the area breakdown of the plugins in Vexii (like the area of IntAlu, Lsu or Branch).
Is there a way to generate plugins as separate verilog modules? Or are there any other…
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### Version
yosys 0.41+126
### On which OS did this happen?
Linux
### Reproduction Steps
Hello,
I encountered a crash issue while using Yosys to synthesize a Verilog file. The specific details…