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## Issue Description
`memory_libmap` pass in Yosys 0.18 and newer would synthesize LUTRAMs unsupported by nextpnr including:
- RAMS32 (manually instantiated)
- RAMD32 (manually instantiated)
- R…
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I have started to work on a better version for my type-based waveform viewer for [Tydi](https://github.com/ccromjongh/Tydi-Chisel) and Chisel-related projects (Tywaves).
My chisel fork: https://git…
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## Steps to reproduce the issue
Build the microwatt soc. It is a mixed language implementation (vhdl and verilog), so you need ghdl and the ghdl plugin.
```
git clone http://github.com/antonbla…
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This issue is a discussion thread and followup about adding Chisel support to TerosHDL extension.
Here I list the initial points I identify as requirement for support:
- Chisel is a DSL based on…
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### Feature Description
With a good number of opensource RTL developers being converted software engineers, a CDC validation option would greatly help improve the quality of IP in opensource domain.
…
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### Is your proposal related to a problem?
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HI
I'd like if you could open a separate git repository with
binaries (bitstream, flash image maybe) of this great example:
https://twitter.com/sylefeb/status/1288053013748289538
emard updated
4 years ago
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The simplest possible block RAM, one that is initialized to all zeroes:
```
import Clash.Prelude
type Addr = Unsigned 13
type Value = Unsigned 8
topEntity
:: Clock System Source
-…
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As the basic FPGA logic has been written, we should document current FPGA sizing and pin connections.
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Is symbolator properly supported for verilog? I got the following error when I ran it on a .v file. I have tried out multiple output formats etc. but no joy.
``` sumanth@LAPTOP-MFGQBV4B:/mnt/g/sy…