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There are some parsers for HDL however all of them have some ridiculous weakness.
I would like to use [hdlConvertor](https://github.com/Nic30/hdlConvertor) because I know that the Python dependency…
Nic30 updated
5 years ago
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This bug was passed to me by someone else, but I am posting it as an issue so we can track it.
Currently pyHDLparser does not parse component declarations inside the architecture of an entity corre…
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Entities and architectures can end with "end some_name;" instead of "end entity;" or "end architecture;" The regex should check for any word (maybe with \w) instead of the specific keywords "entity" …
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The integer modulo (remainder) Operator "%" insn't implemented...
Demo code:
```cpp
#include "intN_t.h"
#pragma MAIN_MHZ test 100.0
int32_t test(int32_t a, int32_t b){
return a % b; /…
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I have a case where a VHDL entity (say vhdl_top) is instantiating a Verilog module with upper-case letters (say VERILOG_MODULE):
VERILOG:
```
module VERILOG_MODULE (
.....
endmodule
```
T…
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Hello,
I wrote a JSON parser for the Hardware Description Language VHDL called [JSON-for-VHDL](https://github.com/Paebbels/JSON-for-VHDL?ts=2). My repository contains 5 projects for 5 different vendo…
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I'm reluctant to call this an issue but I was unable to reach out in an other way. I wanted to ask if there are plans to write any queries locals.scm/highlight.scm/indents.scm
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# Background
I am the maintainer of the [Rust HDL ](https://github.com/VHDL-LS/rust_hdl) project which implements a VHDL parser and semantic analysis as well as a language server. One of the goals fo…
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Hello!
We love your bot in the MiSTer FPGA discord. I have noticed a possible issue recently. Case statements in vhdl do not apparently get syntax highlighting
https://github.com/MiSTer-devel/GB…
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[VHDL/pyVHDLModel](https://github.com/VHDL/pyVHDLModel) is an abstract language model for VHDL, meant to be used as an interface between *any* VHDL parser and projects providing graphical views, refor…