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hdl
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pyHDLParser
Simple Python parser for extracting HDL (VHDL or Verilog) documentation
https://HDL.github.io/pyHDLParser
MIT License
16
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9
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Add support for parsing definition of record
#12
Jenkins047
opened
5 months ago
0
Adding Bluespec Support
#11
iamkarthikbk
opened
6 months ago
0
fix VhdlExtractor.is_array + use setup.cfg + clean
#10
kammoh
opened
2 years ago
0
Update README
#9
vvvverre
closed
2 years ago
0
README is out of date
#8
vvvverre
opened
2 years ago
1
VHDL: parsing component declarations inside entities
#7
vvvverre
opened
2 years ago
3
Python 2 to 3 migration changes: format strings
#6
vvvverre
closed
2 years ago
2
Python 2 code cleanup
#5
michael-etzkorn
opened
2 years ago
0
VHDL parser from andres manelli's fork for entity parsing support
#4
michael-etzkorn
closed
2 years ago
5
Zhelnio's Fork default param extraction fails on 3.10
#3
michael-etzkorn
closed
2 years ago
1
doc: use BuildTheDocs, add CI workflow
#2
umarcor
opened
2 years ago
2
Initial reorganisation
#1
umarcor
opened
2 years ago
9