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ChrisShakkour
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RV32I-MAF-project
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
MIT License
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Trackers integration
#90
ChrisShakkour
closed
2 years ago
0
Trackers integration
#89
ChrisShakkour
closed
2 years ago
0
Load Hazard Unit Hardware race
#88
ChrisShakkour
opened
2 years ago
0
Stack pointer register Tracker (sp)
#87
ChrisShakkour
opened
2 years ago
0
Trackers integration
#85
ChrisShakkour
closed
2 years ago
0
Data memory RTL cleaning
#84
ChrisShakkour
opened
2 years ago
0
Assertions - Signal Indication that something wrong has happened. (Or coverage point - something should happen)
#83
amichai-bd
opened
2 years ago
0
ALU tracker
#82
ChrisShakkour
opened
2 years ago
0
Load Hazzard unit documentation
#81
ChrisShakkour
closed
2 years ago
0
Branch commands validation
#79
ChrisShakkour
closed
2 years ago
0
End of test checkers
#78
ChrisShakkour
opened
2 years ago
0
Load Hazzard validation
#77
ChrisShakkour
opened
2 years ago
0
Branch commands validation
#76
ChrisShakkour
closed
2 years ago
0
RTL simulation automatic flow
#75
ChrisShakkour
opened
2 years ago
0
to add Code simulation run c test using risc-v toolchain elf-run
#74
ChrisShakkour
opened
2 years ago
0
JALR data hazzard validation
#73
ChrisShakkour
closed
2 years ago
1
Boot flow validation
#72
ChrisShakkour
closed
2 years ago
0
Boot flow documentation
#71
ChrisShakkour
closed
2 years ago
0
forwarding unit rtl
#70
shahardror1
closed
2 years ago
0
data hazard
#69
ChrisShakkour
closed
2 years ago
0
dev and methodologies document
#68
ChrisShakkour
closed
2 years ago
0
ALU design module drawing and documentation
#67
ChrisShakkour
closed
2 years ago
0
Forwarding unit Design Drawing and documentation
#66
ChrisShakkour
closed
2 years ago
0
Decode module state machine documentation
#65
ChrisShakkour
opened
2 years ago
0
Branch comparator module Drawing + documentation
#64
ChrisShakkour
closed
2 years ago
0
M-extension multi-cycle machine initial drafts
#63
ChrisShakkour
opened
2 years ago
0
memory Heavy validation test
#62
ChrisShakkour
opened
2 years ago
1
Branch/jump heavy validation Test
#61
ChrisShakkour
closed
2 years ago
1
control hazzard Validation - branch not taken Path
#60
ChrisShakkour
closed
2 years ago
0
control hazzard Design and integration
#59
ChrisShakkour
closed
2 years ago
0
Chris Branch and control hazard integration
#58
ChrisShakkour
closed
2 years ago
0
forwarding load commands from write back stage only
#57
ChrisShakkour
closed
2 years ago
0
data hazard + pipe tracker
#56
shahardror1
closed
2 years ago
0
set alu lsb bit zero for JALR and Branch commands, offset is always even.
#55
ChrisShakkour
closed
2 years ago
1
adding branch commands
#54
ChrisShakkour
closed
2 years ago
0
Chris inst control
#53
ChrisShakkour
closed
2 years ago
0
waves.do files for faster debug
#52
ChrisShakkour
closed
2 years ago
0
single cycle nop insertion on jump/branch commands
#51
ChrisShakkour
closed
2 years ago
1
stalling control signals
#50
ChrisShakkour
opened
2 years ago
0
data hazzard forwarding mechanisim
#49
ChrisShakkour
closed
2 years ago
0
Load store commands
#48
ChrisShakkour
closed
2 years ago
0
Pipeline instruction propagation tracker
#47
ChrisShakkour
closed
2 years ago
0
Crt0 and linker config addr space
#46
ChrisShakkour
closed
2 years ago
0
Own MicroCode for debug use
#45
ChrisShakkour
closed
2 years ago
0
mid semster project reqiurments for VLSI lab (G)
#44
ChrisShakkour
closed
2 years ago
0
data mem tracker
#43
ChrisShakkour
closed
2 years ago
1
Inst fetch tracker
#42
ChrisShakkour
closed
2 years ago
0
Register File tracker
#41
ChrisShakkour
opened
2 years ago
0
add sw,jal,lui commands
#40
shahardror1
closed
2 years ago
0
Latch and race condition detected,
#39
ChrisShakkour
closed
2 years ago
0
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